DS1204V electronic key DS1204V 021798 1/10 features ? cannot be deciphered by reverse engineering ? partitioned memory thwarts pirating ? user-insertable packaging allows personal posses- sion ? exclusive blank keys on request ? appropriate identification can be made with a 64-bit reprogrammable memory ? unreadable 64-bit security match code virtually pre- vents deciphering by exhaustive search with over 10 19 possibilities ? 128 bits of secure read/write memory create addition- al barriers by permitting data changes as often as needed ? rapid erasure of identification security match code and secure read/write memory can occur if tampering is detected ? low-power cmos circuitry ? four million bps data rate ? durable and rugged ? applications include software authorization, gray market software protection, proprietary data, financial transactions, secure personnel areas, and system ac- cess control pin assignment 1.0 in bottom: pin view side DS1204V electronic key dallas 15 see mech. drawings section pin description pin 1 - v cc +5 volts pin 2 - rst reset pin 3 - dq data input/output pin 4 - clk clock pin 5 - gnd ground description the DS1204V electronic key is a miniature security system that stores 64 bits of user-definable identifica- tion code and a 64-bit security match code that protects 128 bits of read/write nonvolatile memory. the 64-bit identification code and the security match code are pro- grammed into the key via a special program mode oper- ation. after programming, the key follows a procedure with a serial format to retrieve or update data. interface cost to a microprocessor is minimized by on-chip circuit- ry that permits data transfer with only three signals: clock (clk), reset (rst ), and data input/output (dq). low pin count and a guided entry for mating receptacle overcome mechanical problems normally encountered with conventional integrated circuit packaging, making the device transportable and user-insertable. operation normal mode the electronic key has two modes of operation: normal and program. the block diagram (see figure 1) illus- trates the main elements of the key when used in the normal mode. to initiate data transfer with the key, rst is taken high and 24 bits are loaded into the command
DS1204V 021798 2/10 register on each low-to-high transition of the clk input. the command register must match the exact bit pattern that defines normal operation for read or write, or com- munications are ignored. if the command register is loaded properly, communications are allowed to contin- ue. the next 64 cycles to the key are reads. data is clocked out of the key on the high-to-low transition of the clock from the identification memory. next, 64 write cycles must be written to the compare register. these 64 bits must match the exact pattern stored in the secu- rity match memory. if a match is not found, access to ad- ditional information is denied. instead, random data is output for the next 128 cycles when reading data. if write cycles are being executed, the write cycles are ignored. if a match is found, access is permitted to a 128-bit read/ write nonvolatile memory. figure 2 is a summary of nor- mal mode operation and figure 3 is a flow chart of the normal mode sequence. block diagram - normal mode figure 1 d/q clk compare register random data rst 128bit secure memory 64bit security match 64bit identification command register control logic sequence - normal mode figure 2 command word 64 read cycles 64 write cycles 128 read or writes secure memory match protocol identification security match
DS1204V 021798 3/10 flow chart - normal mode figure 3 write command protocol read 64 bits identification write 64 bits security match match no stop no output in high z reset high reset low match for read or write output garbled data read or write 128 bits based on protocol secure nv ram program mode the block diagram in figure 4 illustrates the main ele- ments of the key when used in the program mode. to ini- tiate the program mode, rst is driven high and 24 bits are loaded into the command register on each low-to-high transition of the clk input. the command register must match the exact pattern that defines pro- gram operation. if an exact match is not found, the re- mainder of the program cycle is ignored. if the command register is properly loaded, then the 128 bits that follow are written to the identification memory and the security match memory. figure 5 is a summary of program mode operation and figure 6 is a flow chart of program mode operation.
DS1204V 021798 4/10 block diagram - program mode figure 4 d/q clk command register rst control logic 64bit identification 64bit security match sequence - program mode figure 5 command word 64 write cycles 64 write cycles protocol identification security match command word each data transfer for the normal and program mode begins with a three-byte command word as shown in figure 7. as defined, the first byte of the command word specifies whether the 128-bit nonvolatile memory will be written into or read. if any one of the bits of the first byte of the command word fails to meet the exact pattern of read or write, the data transfer will be aborted. the 8-bit pattern for read is 01100010. the pattern for write is 10011101. the first two bits of the second byte of the command word specify whether the data transfer to follow is a program or normal cycle. the bit pattern for program is 0 in bit 0 and 1 in bit 1. the program mode can be selected only when the first byte of the command word specifies a write. if the program mode is specified and the first byte of the command word does not specify a write, data transfer will be aborted. the bit pattern that selects the normal mode of operation is 1 in bit 0 and 0 in bit 1. the other two possible combinations for the first two bits of byte 2 will cause data transfer to abort. the remaining six bits of byte 2 and the first seven bits of byte 3 form unique patterns that allow multiple keys to reside on a common bus. as such, each respective code pattern must be written exactly for a given device or data transfer will abort. dallas semiconductor has five patterns available as standard products per the chart in figure 7. each pattern corresponds to a specific part number. under special contract with dallas semi- conductor, the user can specify any bit pattern other than those specified as unavailable. the bit pattern as defined by the user must be written exactly or data transfer will abort. the last bit of byte 3 of the command word must be written to logic 1 or data transfer will abort. note: contact the dallas semiconductor sales office for a spe- cial command word code assignment that makes possi- ble an exclusive blank key.
DS1204V 021798 5/10 flow chart - program mode figure 6 write command protocol identification write 64 bits security match stop no output in high z write 64 bits reset low reset high match program mode reset and clock control all data transfers are initiated by driving the rst input high. the rst input serves three functions. first, it turns on control logic, which allows access to the command register for the command sequence. second, the rst signal provides a power source for the cycle to follow. to meet this requirement, a drive source for rst of 2 ma @ 3.5 volts is required. however, if the v cc pin is con- nected to a 5-volt source within nominal limits, the rst is not used as a source of power and input levels revert to normal v ih and v il inputs with a drive current require- ment of 500 m a. third, the rst signal provides a meth- od of terminating data transfer. a clock cycle is a sequence of a falling edge followed by a rising edge. for data inputs, the data must be valid during the rising edge of a clock cycle. command bits and data bits are input on the rising edge of the clock and data bits are output on the falling edge of the clock. the rising edge of the clock returns the dq pin to a high im- pedance state. all data transfer terminates if the rst pin is low and the dq pin goes to a high impedance state. when data transfer to the key is terminated using rst , the transition of rst must occur while the clock is at a high level to avoid disturbing the last bit of data. data transfer is illustrated in figure 8 for normal mode and figure 9 for program mode.
DS1204V 021798 6/10 command word figure 7 xxx xxx 1 23 byte 3 byte 2 byte 1 0 00000 00000 p 11 0000 00000 p 11 1 0 0 0 0 DS1204Vg01 DS1204Vg02 DS1204Vg03 DS1204Vg04 DS1204Vg05 byte 2 byte 3 byte 2 byte 3 w w ww w xxxxxx p x r r r r r rr w w w r p p p byte 2 byte 3 byte 2 byte 3 byte 2 byte 3 00001 00000 p 11 0000 00000 p 11 1 0 0 1 0 p p 0001 00000 p 11 0 0 0 p key connections the key is designed to be plugged into a standard 5-pin, 0.1-inch center sip receptacle (samtec ss105 or equivalent). a guide is provided to prevent the key from being plugged in backwards and aid in alignment of the receptacle. for portable applications, contact to the key pins can be determined to ensure connection integrity before data transfer begins. clk, rst , and dq all have internal 20k ohm pulldown resistors to ground that can be sensed by a reading device.
DS1204V 021798 7/10 data transfer - normal mode figure 8 dq127 dq126 1 q63 dq0 q0 d63 d0 0 123 clock write read command read/write reset 128 bits 64 bits word 64 bits r/w r /w data transfer - program mode figure 9 1 q63 01 23 clock 2 q0 q1 q62 q0 q1 q62 q63 clk reset write command 64 bits word write 64 bits r/w r /w
DS1204V 021798 8/10 absolute maximum ratings* voltage on any pin relative to ground -0.5v to +7.0v operating temperature 0 c to 70 c storage temperature -40 c to +70 c * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes logic 1 v ih 2.0 v 1, 8, 10 logic 0 v il -0.3 +0.8 v 1 reset logic 1 v ihe 3.5 v 1, 9, 11 supply v cc 4.5 5.0 5.5 v 1 dc electrical characteristics (0 c to 70 c; v cc = 5v + 10%) parameter symbol min typ max units notes input leakage i il +500 m a 4 output leakage i lo +500 m a output current @2.4v i oh -1 ma output current @0.4v i ol +2 ma rst input resistance z rst 10 60 k ohms d/q input resistance z dq 10 60 k ohms clk input resistance z clk 10 60 k ohms rst current @3.0v i rst 2 ma 6, 9, 13 active current i cc1 6 ma 6 standby current i cc2 2.5 ma 6 capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 5 pf output capacitance c out 7 pf
DS1204V 021798 9/10 ac electrical characteristics (0 c to 70 c, v cc = 5v + 10%) parameter symbol min typ max units notes data to clk setup t dc 35 ns 2, 7 clk to data hold t cdh 40 ns 2, 7 clk to data delay t cdd 100 ns 2, 3, 5, 7 clk low time t cl 125 ns 2, 7 clk high time t ch 125 ns 2, 7 clk frequency f clk dc 4.0 mhz 2, 7 clk rise & fall t r , t f 500 ns 2, 7 rst to clk setup t cc 1 m s 2, 7 clk to rst hold t cch 40 ns 2, 7 rst inactive time t cwh 125 ns 2, 7, 14 rst to i/o high z t cdz 50 ns 2, 7 timing diagram: write data clock data input/output reset r /w r/w r/w t ch t cdh t dc t cc t cl t r t f t cwh t cch timing diagram: read data clock reset r /w t cc t cwh t cdz t cdd t dc
DS1204V 021798 10/10 notes: 1. all voltages are referenced to gnd. 2. measured at v ih = 2.0 or v il = .8v and 10ns maximum rise and fall time. 3. measured at v oh = 2.4 volts and v ol = 0.4 volts. 4. for clk, d/q, and rst . 5. load capacitance = 50 pf. 6. measured with outputs open. 7. measured at v ih of rst > 3.5v when rst supplies power. 8. logic 1 maximum is v cc + 0.3 volts if the v cc pin supplies power and rst + 0.3 volts if the rst pin supplies power. 9. applies to rst when v cc < 3.5v. 10. input levels apply to clk, dq, and rst while v cc is within nominal limits. when v cc is not connected to the key, then rst input reverts to v ihe . 11. rst logic 1 maximum is v cc + 0.3 volts if the v cc pin supplies power and 5.5 volts maximum if rst supplies power. 12. each DS1204V is marked with a 4-digit code aabb. aa designates the year of manufacture. bb designates the week of manufacture. 13. average ac rst current can be determined using the following formula: i total = 2 + i load dc + (4 x 10- 3 ) (cl + 140) f i total and i load are in ma; c l is in pf; f is in mhz. applying the above formula, a load capacitance of 50 pf running at a frequency of 4.0 mhz gives an i total of 5 ma. 14. when rst is supplying power t cwh must be increased to100 ms average.
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